New and different types of DRAM array architecture as well as tighter design specifications for integrated circuit chip size require new designs for implementing redundant row lines and the circuits for enabling them. The provision of redundant row lines allows faulty word lines to be replaced in order to repair the DRAM to a sellable status.
One conventional row redundancy method is to blow a fuse between a bad word line and its respective decoder circuit, thus disabling the faulty word line. Fuses are also blown in a redundant decoder in order to program the redundant decoder to connect a redundant word line to a global drive/boot signal line when the redundant address is selected. This replaces the bad word line or row line with a redundant word line. A disadvantage of this conventional method is that each word line must have a fuse located between it and its row decoder. This can take up large amounts of space and may not even be possible to implement on chips with small row pitches. This method is however efficient since only the bad word line is replaced and not several other good word lines along with it.
Other conventional methods of enabling redundant row lines and disabling faulty word lines will be discussed below, but may be briefly reviewed here. In order to program a redundant row line according to another method, a fuse is blown in the normal decoder to disable it and all word lines connected to it. Fuses are then blown in a redundant decoder to program it to replace the decoder and its bad word line. Although only one fuse is needed for every four word lines, this method is relatively inefficient in replacing bad word lines since one bad word line will cause three other good word lines to be replaced in addition to itself.
A third conventional method is to blow fuses in a redundant decoder in order to program it to the address of the bad word line. Then, once this redundant decoder detects the redundant address, it completely disables a global drive/boot signal generator that would drive the bad word line through a decoder, and enables a redundant drive/boot generator which then drives a redundant word line through the redundant decoder. Therefore, the replaced word line does not become active since the normal drive/boot generator is disabled for this cycle. Although this method does not need a fuse for each word line or even for each row decoder, it is disadvantageous in that a separate redundant drive/boot generator is required in the peripheral area of the chip. In view of the drawbacks of each of these conventional methods, a need has arisen for a redundancy scheme that will have the capability of replacing a single word line but nonetheless does not require a fuse for each row or an additional drive/boot signal generator.